KT AI-MAKER_KET 구성품은 다음과 같다.

가장 중요한 Raspberry Pi 3B(3B+를 권장하지만, 본인은 3B를 보유).

그 Spec은 다음과 같다.

https://www.raspberrypi.org/products/raspberry-pi-3-model-b/

 

Buy a Raspberry Pi 3 Model B – Raspberry Pi

The Raspberry Pi 3 Model B is the earliest model of the third-generation Raspberry Pi. It replaced the Raspberry Pi 2 Model B in February 2016. See also the Raspberry Pi 3 Model B+, the latest product in the Raspberry Pi 3 range. Quad Core 1.2GHz Broadcom

www.raspberrypi.org

Specification

The Raspberry Pi 3 Model B is the earliest model of the third-generation Raspberry Pi. It replaced the Raspberry Pi 2 Model B in February 2016. See also the Raspberry Pi 3 Model B+, the latest product in the Raspberry Pi 3 range.

  • Quad Core 1.2GHz Broadcom BCM2837 64bit CPU
  • 1GB RAM
  • BCM43438 wireless LAN and Bluetooth Low Energy (BLE) on board
  • 100 Base Ethernet
  • 40-pin extended GPIO
  • 4 USB 2 ports
  • 4 Pole stereo output and composite video port
  • Full size HDMI
  • CSI camera port for connecting a Raspberry Pi camera
  • DSI display port for connecting a Raspberry Pi touchscreen display
  • Micro SD port for loading your operating system and storing data
  • Upgraded switched Micro USB power source up to 2.5A

BCM2837을 Main Core로 사용하고 있다. BCM2837의 Spec은 다음과 같다.

http://jake.dothome.co.kr/raspberry-hw/

 

Raspberry SoC 스펙

라즈베리 파이 3(Raspberry Pi 3 모델B)  SoC: BCM2837 Silicon die: BCM2710 ARM Core CPU Family: ARM Coretex-A53 (64bit ARMv8-A 아키텍처) Quad-core (1.2Ghz) Spupport 40bit physical address GPU Core BCM VideoCore IV @ 300 MHz L1 Cache Instruction Cache 32KB(VIPT, 2 way, 6

jake.dothome.co.kr

  • SoC: BCM2837
    • Silicon die: BCM2710
    • ARM Core
      • CPU Family: ARM Coretex-A53 (64bit ARMv8-A 아키텍처)
      • Quad-core (1.2Ghz)
      • Spupport 40bit physical address
    • GPU Core
      • BCM VideoCore IV @ 300 MHz
    • L1 Cache
      • Instruction Cache
        • 32KB(VIPT, 2 way, 64 bytes per cache line)
      • Data Cache
        • 32KB(PIPT, 4 way, 64 bytes per cache line) with STB(merging STore Buffer)
        • MOESI cache coherent between cores
    • L2 Cache:
      • Unification(I+D) Cache
        • 512KB for ARM(16 way, 64 bytes per cache line)
    •  TLB
      •  micro-TLB
        • micro I-TLB
          • fully-associative 10 entry
        • micro-D-TLB
          • fully-associative 10 entry
      • Unified Main TLB
        • 4-way 512 entry
        • 4-way 64 entry walk cache
        • 4-way 64 entry IPA(Intermediate Physical Address) cache
  •  RAM
    • 1GB LPDDR2 (GPU랑 공유)

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